http://ea.donntu.ru/handle/123456789/68 Свідоцтво про державну реєстрацію: КВ № 7374 від 03.06.2003 Mon, 20 Apr 2026 02:22:55 GMT 2026-04-20T02:22:55Z http://ea.donntu.ru/handle/123456789/30915 Title: Алгоритм вокселизации сферического треугольника Authors: Башков, Е.А.; Непочатая, С.А.; Башков, Є.О.; Непочата, С.О.; Bashkov, Ye.A.; Nepochataya, S.A. Abstract: Поставлена задача воксельного разложения сферического треугольника в видеопамяти трехмерного дисплея и предложен метод ее решения. Рассмотрен алгоритм воксельного разложения сферического треугольника и некоторые его модификации. Представлены результаты численных экспериментов. Description: A problem of the spherical triangle voxel representation in volumetric 3D display memory has been considered. The spherical triangle is defined by the center of the given radius sphere and three points lying on the surface. The problem is reduced to finding the set of voxels, each of which a) has at least one point in common with the sphere, b) projection of the voxel center belongs to the spherical triangle and c) has no more than 8 ne ighbors. A general algorithm for solving the problem was suggested. Two approaches to solve the subtasks of checking of belonging of voxel to the spherical triangle were considered a) comparing the sum of the areas of the triangles formed by the checked voxel and the area of the original triangle and b) estimating of the given voxel position relative to three planes formed by the center of the sphere and three given vertices. Numerical experiments and comparative analysis of the generation time of arbitrary triangles was studied. It was concluded that the second approach to the verification of voxel accessories is faster on average by 15 %. Wed, 01 Jan 2014 00:00:00 GMT http://ea.donntu.ru/handle/123456789/30915 2014-01-01T00:00:00Z http://ea.donntu.ru/handle/123456789/30914 Title: Реализация схемы автомата Мили в базисе гибридных FPGA Authors: Баркалов, А.А.; Мальчева, Р.В.; Баркалов, А.А.; Баркалов, О.О.; Баркалов, О.О.; Barkalov, A.A.; Malcheva, R.V.; Barkalov, A.A. Abstract: Предложен метод уменьшения аппаратурных затрат в схеме микропрограммного автомата Мили, ориентированный на технологию гибридных FPGA. Метод основан на использовании модели PR-автомата и реализации системы микроопераций на встроенных блоках PLA. Такой подход позволяет уменьшить число LUT элементов в схеме автомата. Приведены условия применения предложенного метода. Description: The model of Mealy finite state machine (FSM) is widely used for implementing the control units. Nowadays, the hybrid field – programmable gate arrays (HFPGA) are applied for implementing complex digital systems. FPGA have the benefits of the hardware speed and the software flexibility. The last decade has seen ever increasing application areas for FPGAs. Modern FPGAs currently accommodate more than ten million gates with clock rates up to 600 MHz. As a rule, the FPGAs include look-up table (LUT) elements and embedded PLA blocks (programmable logic array). One of the important problems connected with FSM design is the reduction of the number of LUTs in an FSM’s logic circuit. The solution of this problem allows decreasing of the number of interconnections among the LUTs. In turn, it leads to increasing of the performance and decreasing of the power dissipation. Using PLAs instead of LUTs is one of the possible ways for solving this problem. In the case of Mealy FSM, the system of microoperations could be implemented with PLAs. But it leads to the encoding of collections of microoperations and using some resources of a chip for generating these additional variables. A method is proposed for reducing the hardware amount in logic circuit of Mealy FSM. The method targets the technology of HFPGA. The method is based on using the model of PR-automaton and implementing the system of microoperations with embedded PLAs. This approach allows reducing the number of LUTs in the FSM’s circuit. The conditions are shown for using the proposed method. The example of FSM synthesis is given with applying the proposed approach. An application of proposed method allows the average decrease for the number of LUTs up to 32%. The scientific novelty of the proposed method is reduced to adaptation of the design method for PR-automaton to the specifics of HFPGAs. The practical meaning of the method is determined by reducing for the number of LUTs in an FSM logic circuit in comparison with known methods. The further direction of the research is connected with development of state assignment methods leading to decreasing of the number of LUTs in the circuit of LUTer. Wed, 01 Jan 2014 00:00:00 GMT http://ea.donntu.ru/handle/123456789/30914 2014-01-01T00:00:00Z http://ea.donntu.ru/handle/123456789/30913 Title: Информационная технология оценки достоверности данных при интеграции web-ориентированных систем Authors: Брагина, Т.И.; Брагіна, Т.І.; Bragina, T.I. Abstract: В данной работе рассматривается предложенная риск-ориентированная информационная технология оценки достоверности данных при интеграции web-ориентированных информационных систем, позволяющая снизить тестовое покрытие при интеграции баз данных web-ориентированных информационных систем на основании априорного анализа рисков. Description: In this paper the risk-oriented information technology for data accuracy assessment within integration of web-based systems was proposed by the author, which allows reducing test coverage within database integrating for web-oriented information systems based on a priori risk analysis. Presented information technology based on a database verification model is characterized by having a plurality of parity relations of corrective tests containing the errors treatment plan with risks for database entities attributes. This connection allows identifying automatically the most critical data tuples and test methods aimed at controlling the most probabile risks in order to fix a set of known bugs, as well as get information about undiscovered errors. The proposed information technology presents several possibilities: –information on selected risks will allow determining the most critical modules and tuples for testing; –screening corrective tests will automate the time-consuming process of bringing data to the required format and consistency; – continuous monitoring of new unexplored errors will expand the base of tests and, consequently, reduce one of the most common causes of errors in the application – the emergence of unanticipated and hence unexplored combinations of inputs. Automation of the proposed risk-based method of integrated databases testing within information technology for data accuracy assessment within integration of web-based systems reduced the time spent by 17% by reducing test coverage, maintaining the level of undetected errors at an acceptable level (0.1% of erroneous data in relation to the total number of data in the database). Wed, 01 Jan 2014 00:00:00 GMT http://ea.donntu.ru/handle/123456789/30913 2014-01-01T00:00:00Z http://ea.donntu.ru/handle/123456789/30912 Title: Реализация КМУУ с элементарными цепями на гибридных FPGA Authors: Баркалов, А.А.; Титаренко, Л.А.; Ефименко, К.Н.; Зеленева, И.Я.; Barkalov, A.A.; Titarenko, L.A.; Efimenko, K.N.; Zelenjova, I.J.; Баркалов, О.О.; Титаренко, Л.О.; Єфіменко, К.М.; Зеленьова, I.Я. Abstract: Предлагается метод уменьшения аппаратурных затрат в схеме КМУУ с элементарными цепями, ориентированный на технологию гибридных FPGA. Метод основан на замене LUT-элементов схемой, состоящей из встроенных блоков PLA (programmable logic array), что возможно при использовании данной технологии. Такой подход позволит уменьшить число LUT элементов в схеме адресации КМУУ. Приведен пример применения предложенного метода. Description: The proposed method is oriented to reducing the hardware amount of the composite miсroprograming control unit (CMCU) scheme with elementary chains, using the technology of hybrid FPGA. To optimize the hardware cost in the scheme of the control device in the FPGA it is necessary to reduce the number of arguments and implemented systems in terms of Boolean functions. The idea of the proposed in this paper method is based on the two sources of codes of classes of pseudoequivalent elementary operational linear chains (EOLC) and replacement of LUT-element for a circuit consisting of embedded blocks PLA (programmable logic array). This is possible by using hybrid technology FPGA, which is actively developing now. The proposed structure of com-positional microprogram control unit uses the following resources of crystal hybrid FPGA: LUT-elements for the register and the counter of transition address, PLA blocks for scheme of microinstructions addressing in control memory. The control memory is implemented on reconfigurable memory blocks EMB. These blocks have a specific number of outputs and inputs. At the same time there is a high probability of having unused outputs of EMB included in the control memory. In this paper we propose a method for the synthesis of CMCU, comprising the steps of: forming the set of elementary linear chains for a given flow-chart of the control algorithm; op-timal encoding of elementary chains and encoding of their components; formation of sets of pseudoequivalent chains, their optimal encoding; formation of the transition table of compositional microprograming control unit; formation of control memory content; synthesis of scheme CMCU in a given basis. An example of application of the proposed method is given. Scientific novelty of the proposed method is to use features CMCU (classes of pseudoequivalent EOLC) and hybrid FPGA (fixed number of block outputs and a built- EMB blocks PLA) to reduce the number of elements in the LUT-scheme CMCU with elementary chains. The practical significance of the method is to reduce the chip area FPGA, occupied by CMCU scheme that allows getting schemes which have a lower cost than prior known analogues. Wed, 01 Jan 2014 00:00:00 GMT http://ea.donntu.ru/handle/123456789/30912 2014-01-01T00:00:00Z